1. Field of the Invention
The present invention relates to a multilayer chip capacitor, more particularly, which is suitably used as a decoupling capacitor of a Micro Processor Unit (MPU) and is capable of reducing Equivalent Series Inductance (ESL).
2. Description of the Related Art
In general, a multilayer chip capacitor (MLCC) includes a plurality of dielectric layers made of ceramics, and internal electrodes interleaved therebetween. The multilayer chip capacitor is small-sized and capable of high capacitance, thus broadly used as capacitive parts of various electronic devices. Especially, the multilayer chip capacitor is extensively used as a decoupling capacitor installed between a semiconductor chip and an electric source in power supply circuits such as a Large Scale Integration (LSI) device.
The capacitor used as the decoupling capacitor needs to have lower ESL to inhibit rapid current change and stabilize the power supply circuits. Higher-frequency and higher-current trend of the MPU has increased such demand. A method for reducing ESL of the multilayer chip capacitor is disclosed in U.S. Pat. No. 5,880,925. The document teaches a method for disposing leads of a positive internal electrode adjacent to those of a negative internal electrode in an interdigitated arrangement. As an example of the conventional technique, FIGS. 1a to 1c show a multilayer chip capacitor in which adjacent leads of first and second internal electrodes having the opposite polarity are disposed alternately.
FIG. 1a is an exploded perspective view illustrating an internal electrode structure of a conventional multilayer chip capacitor. FIG. 1b is a perspective view illustrating the exterior of a conventional multilayer chip capacitor 10 employing the internal electrode structure of FIG. 1a. FIG. 1c is a perspective view illustrating a partial internal structure of the multilayer chip capacitor of FIG. 1b. Dielectric layers 11a, 11b, 12a and 12b are not illustrated in FIG. 1c. Referring to FIGS. 1a and 1b, first internal electrodes 13 (13a, 13b) are formed on respective dielectric layers 11a, 11b and second internal electrodes 14 (14a, 14b) are formed on respective dielectric layers 12a and 12b. Four leads 15a, 15b, 16a and 16b are formed on the respective electrodes 13a, 13b, 14a and 14b. These dielectric layers are stacked alternately to constitute a capacitor body 20. To manufacture the multilayer chip capacitor 10, the capacitor body 20 is compressed and fired, and in addition, external terminal electrodes 17 and 18 are formed to connect to the respective leads 15a, 15b, 16a and 16b. 
At this time, the first internal electrodes 13a and 13b exhibit the same polarity (likewise, the second internal electrodes 14a and 14b exhibit the same polarity), however the opposite polarity with respect to the second internal electrodes 14a and 14b. In the adjacent leads 15a and 16a having the opposite polarity, currents flow in opposite directions as indicated with an arrow (see reference sign 1a). Therefore, magnetic flux generated by a high-frequency current is partially cancelled, decreasing ESL of the capacitor 10.
As shown in FIG. 1c, the vertically adjacent two leads of the first internal electrodes 13a and 13b extend in parallel (in the same direction) to an external electrode 17. Thus, as shown in FIG. b, in the vertically adjacent leads 15a and 15b having the same polarity 5a and 15b, currents flow in the same direction (indicated with an arrow). In this fashion, currents flowing in the same direction through the leads 15a, 15b generate strong mutual inductance. This mutual inductance renders it hard to reduce ESL sufficiently. To be used as the decoupling capacitor for the MPU, the multilayer chip capacitor needs to exhibit lower ESL.